FIG. 5 illustrates an example of a data transmission circuit in a related art. A data transmission circuit 100 includes a PLL (Phase Locked Loop) circuit 101, dividers 102 to 104, a FIFO (First-In First-Out) 105, multiplexers (MUXs) 106 to 109, and an output driver 110. The PLL circuit 101 generates a clock signal CKA (frequency: 20 GHz) based on a clock signal REF_CK (frequency: 625 MHz). The divider 102 frequency-divides the clock signal CKA into ½ to generate a clock signal CKB (frequency: 10 GHz). The divider 103 frequency-divides the clock signal CKB into ½ to generate a clock signal CKC (frequency: 5 GHz). The divider 104 frequency-divides the clock signal CKC into ½ to generate a clock signal CKD (frequency: 2.5 GHz).
The FIFO 105 sequentially acquires parallel data signals USR_DT (16 bits) in synchronization with a clock signal USR_CK (frequency: 2.5 GHz), and outputs them as data signals DTE (16 bits) in response to a rising transition of the clock signal CKD in order from the earliest acquired data signals. The multiplexer 106 converts the data signal DTE into data signals DTD (8 bits) synchronized with the clock signal CKD. The multiplexer 107 converts the data signals DTD into data signals DTC (4 bits) synchronized with the clock signal CKC. The multiplexer 108 converts the data signals DTC into data signals DTB (2 bits) synchronized with the clock signal CKB. The multiplexer 109 converts the data signals DTB into a data signal DTA (1 bit) synchronized with the clock signal CKA. The output driver 110 receives the data signal DTA and outputs it as a serial data signal TX_DT.
FIG. 6 illustrates a part of the data transmission circuit of FIG. 5. The divider 102 includes a flip-flop FD and an inverter INV. In synchronization with a rising transition of the clock signal CkA supplied from the PLL circuit 101 (FIG. 5), the flip-flop FD acquires an output signal of the inverter INV and outputs it. The inverter INV inverts the output signal of the flip-flop FD and outputs it. By such a configuration, the clock signal CKB formed by frequency-dividing the clock signal CKA into ½ is generated.
The multiplexer 108 includes latch circuits LM0 to LM9 and selectors SEL0 and SELL for converting 4-bit data signals DTC0 to DTC3 supplied from the multiplexer 107 (FIG. 5) into 2-bit data signals DTB0 and DTB1 synchronized with the clock signal CKB. In synchronization with a rising transition of the clock signal CKB, the latch circuit LM0 acquires the data signal DTC0 and outputs it. In synchronization with a falling transition of the clock signal CKB, the latch circuit LM1 acquires an output signal of the latch circuit LM0 and outputs it. In synchronization with a rising transition of the clock signal CKB, the latch circuit LM2 acquires the data signal DTC2 and outputs it. In synchronization with a falling transition of the clock signal CKB, the latch circuit LM3 acquires an output signal of the latch circuit LM2 and outputs it. In synchronization with a rising transition of the clock signal CKB, the latch circuit LM4 acquires an output signal of the latch circuit LM3 and outputs it. The selector SEL0 selects an output signal of the latch circuit LM1 to output it as the data signal DTB0 during a high level period of the clock signal CKB, and selects an output signal of the latch circuit LM4 to output it as the data signal DTB0 during a low level period of the clock signal CKB.
In synchronization with a rising transition of the clock signal CKB, the latch circuit LM5 acquires the data signal DTC1 and outputs it. In synchronization with a falling transition of the clock signal CKB, the latch circuit LM6 acquires an output signal of the latch circuit LM5 and outputs it. In synchronization with a rising transition of the clock signal CKB, the latch circuit LM7 acquires the data signal DTC3 and outputs it. In synchronization with a falling transition of the clock signal CKB, the latch circuit LM8 acquires an output signal of the latch circuit LM7 and outputs it. In synchronization with a rising transition of the clock signal CKB, the latch circuit LM9 acquires an output signal of the latch circuit LM8 and outputs it. The selector SEL1 selects an output signal of the latch circuit LM6 to output it as the data signal DTB1 during a high level period of the clock signal CKB, and selects an output signal of the latch circuit LM9 to output it as the data signal DTB1 during a low level period of the clock signal CKB. By the configuration as described above, the 4-bit data signals DTC0 to DTC3 are converted into the 2-bit data signals DTB0 and DTB1 synchronized with the clock signal CKB.
The multiplexer 109 includes latch circuits LM10 to LM14 and a selector SEL2 for converting the 2-bit data signals DTB0 and DTB1 into 1-bit data signal DTA synchronized with the clock signal CKA. In synchronization with a rising transition of the clock signal CKA, the latch circuit LM10 acquires the data signal DTB0 and outputs it. In synchronization with a falling transition of the clock signal CKA, the latch circuit LM11 acquires an output signal of the latch circuit LM10 and outputs it. In synchronization with a rising transition of the clock signal CKA, the latch circuit LM12 acquires the data signal DTB1 and outputs it. In synchronization with a failing transition of the clock signal CKA, the latch circuit LM13 acquires an output signal of the latch circuit LM12 and outputs it. In synchronization with a rising transition of the clock signal CKA, the latch circuit LM14 acquires an output signal of the latch circuit LM13 and outputs it. The selector SEL2 selects an output signal of the latch circuit LM11 to output it as the data signal DTA during a high level period of the clock signal CKA, and selects an output signal of the latch circuit LM14 to output it as the data signal DTA during a low level period of the clock signal CKA. By the configuration as described above, the 2-bit data signals DTB0 and DTB1 are converted into the 1-bit data signal DTA synchronized with the clock signal CKA.
FIG. 7 and FIG. 8 illustrate a state of data communication between the multiplexers in FIG. 6. A transmission timing of the data signals DTB0 and DTB1 in the multiplexer 108 is defined by the rising transition or the failing transition of the clock signal CKB, and a reception timing of the data signals DTB0 and DTB1 in the multiplexer 109 is defined by the rising transition of the clock signal CKA. Therefore, in order to securely conduct the data communication between the multiplexers 108 and 109, a sum of a delay time t1 from an occurrence of the rising transition of the clock signal CKA to an occurrence of the rising transition or the failing transition of the clock signal CKB in the divider 102 and a delay time t2 from an occurrence of the rising transition or the falling transition of the clock signal CKB until a determination of the data signals DTB0 and DTB1 in the multiplexer 108, has to be shorter than a cycle T of the clock signal CKA.
As illustrated in FIG. 7, when the delay times t1 and t2 are short and there is a sufficient timing margin in a phase relationship among the clock signal CKA and the data signals DTB0 and DTB1, the data communication is correctly conducted between the multiplexers 108 and 109. Meanwhile, as illustrated in FIG. 8, when the delay times t1 and t2 are long and there is no sufficient timing margin in the phase relationship among the clock signal CKA and the data signals DTB0 and DTB1, there is a possibility that the data signals DTB0 and DTB1 are not determined at the time of the occurrence of the rising transition of the clock signal CKA, and in that case, the multiplexer 109 (latch circuits LM10 and LM12) cannot correctly receive the data signals DTB0 and DTB1.
Further, a technology relevant to a parallel-to-serial conversion circuit which converts parallel data signals into a serial data signal is disclosed in, for example, Patent Documents 1 and 2.
Patent Document 1: Japanese Laid-open Patent Publication No. 08-056240
Patent Document 2: International Publication Pamphlet No. WO 03/028221
Recently, an information amount to be processed tends to be increased in computer (information processing) and information communication fields, and in order to deal with the increase in the information amount, a data transfer rate (data communication speed) among LSIs configuring a system has been increased. Even though only on a research level, a CMOS (Complementary Metal Oxide Semiconductor)—10 Gbps transceiver was announced in 2002. Subsequently, an attention has been paid to a research regarding a CMOS-40 Gbps transceiver. In a region in which a high data transfer rate is required, a leading-edge technology is applied and, for example, regarding the CMOS-40 Gbps transceiver, a research has been carried out by assuming a technology of 0.1 μm or less.
In a data communication system to which a high data transfer rate is required, there is a need to increase a frequency of a clock signal inside a LSI. Further, in accordance with a microfabrication of a semiconductor process, a performance of a transistor is improved, but, a manufacturing variance becomes quite large. Conventionally, circuit blocks that conduct the data communication were designed to be brought close to one another as much as possible in a layout design of the LSI, to thereby secure a timing margin at the time of receiving data. However, owing to the improvement in data transfer rate, the increase in manufacturing variance, and the like, such a method almost reaches its limits. Specifically, it has been getting difficult to securely conduct the data communication between the multiplexers as illustrated in FIG. 8 with the use of the data transmission circuit illustrated in FIG. 5.
Further, a parallel-to-serial conversion circuit of Patent Document 1 includes a plurality of registers that acquire parallel data signals, a plurality of AND gates that receive an output signal of a corresponding register among the plurality of registers and a corresponding clock signal among a plurality of clock signals having mutually different phases, and OR gates that generate a serial data signal from output signals of the plurality of AND gates. In the parallel-to-serial conversion circuit of Patent Document 1, the AND gate relating to the serial data signal is sequentially switched, so that a variation in drivability of the AND gates and a mutual influence among the AND gates occurred at the time of switching the AND gates are likely to appear on an eye pattern of the serial data signal. Accordingly, the circuit is not suitably used when a high data transfer rate is required.
A parallel-to-serial conversion circuit of Patent Document 2 includes a plurality of switch circuits that output corresponding bits of parallel data signals for a period of time corresponding to a phase difference of a corresponding pair of clock signals among a plurality of clock signals having mutually different phases, and an adder that adds output signals of the plurality of switch circuits to generate a serial data signal. In the parallel-to-serial conversion circuit of Patent Document 2, the switch circuit relating to the serial data signal is sequentially switched, so that, for the same reason as that of the parallel-to-serial conversion circuit of Patent Document 1, the conversion circuit is not suitably used when a high data transfer rate is required.
A proposition of the embodiment is to provide a technology with which data communication among internal elements in a data transmission circuit is securely conducted regardless of the improvement in data transfer rate, the increase in manufacturing variance, the variation in power supply voltage and temperature, and the like.